arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask

Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
index 813dff2153b13bab572326a3e4d1b49c37fe279d..297f9e1999d068fc3da6dd897b96f8ded36bc355 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -146,9 +146,9 @@ struct socfpga_system_manager {
 #define SYSMGR_FPGAINTF_SDMMC  BIT(8)
 #define SYSMGR_FPGAINTF_SPIM0  BIT(16)
 #define SYSMGR_FPGAINTF_SPIM1  BIT(24)
-#define SYSMGR_FPGAINTF_EMAC0  (0x11 << 0)
-#define SYSMGR_FPGAINTF_EMAC1  (0x11 << 8)
-#define SYSMGR_FPGAINTF_EMAC2  (0x11 << 16)
+#define SYSMGR_FPGAINTF_EMAC0  BIT(0)
+#define SYSMGR_FPGAINTF_EMAC1  BIT(8)
+#define SYSMGR_FPGAINTF_EMAC2  BIT(16)
 
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT     4
 #define SYSMGR_SDMMC_DRVSEL_SHIFT      0