* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
* ZynqMP does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {
* Versal does not set phase for <=25MHz clock.
* If degrees is zero, no need to do anything.
*/
- if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300 ||
- timing == MMC_TIMING_LEGACY ||
- timing == MMC_TIMING_UHS_SDR12 || !degrees)
+ if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
return 0;
switch (timing) {