clk: zynqmp: Add set_rate support for display clocks

If "assigned-clock-rates" property is included in the
device tree, display driver probe is getting failed, as dp_video_ref
till dp_stc_ref clocks are missing from set rate function, adding
them to fix the probe failure.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240711082939.29260-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 97f3b999d7c8b510328bdc54bfd56a0b9d5b8d12..a8239e228cf6a916b8a8edd5400e69a0851f1869 100644 (file)
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -726,6 +726,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
        case gem_tsu:
        case qspi_ref ... can1_ref:
        case usb0_bus_ref ... usb3_dual_ref:
+       case dp_video_ref ... dp_stc_ref:
                return zynqmp_clk_set_peripheral_rate(priv, id,
                                                      rate, two_divs);
        default: