The bus clock and memory clock are unlikely to go above 4GHz for now, so
reduce the field size to 32 bits.
Signed-off-by: Simon Glass <sjg@chromium.org>
{
ar934x_update_clock();
printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
- printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
- printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
+ printf("Memory: %8d MHz\n", gd->mem_clk / 1000000);
+ printf("AHB: %8d MHz\n", gd->bus_clk / 1000000);
return 0;
}
gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
- debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
+ debug("%s: cpu: %lu, bus: %u\n", __func__, gd->cpu_clk, gd->bus_clk);
return 0;
}
/**
* @bus_clk: platform clock rate in Hz
*/
- unsigned long bus_clk;
+ unsigned int bus_clk;
/**
* @mem_clk: memory clock rate in Hz
*/
- unsigned long mem_clk;
+ unsigned int mem_clk;
/**
* @env_addr: address of environment structure
*