bool "Nios II architecture"
select CPU
select DM
+ imply DM_EVENT
select OF_CONTROL
select SUPPORT_OF_CONTROL
imply CMD_DM
select DM
imply DM_SERIAL
imply DM_ETH
+ imply DM_EVENT
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply CMD_SF_TEST
imply CMD_ZBOOT
imply DM_ETH
+ imply DM_EVENT
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
select SUPPORT_SPL
imply TI_SYSC if DM && OF_CONTROL
imply FIT
+ imply DM_EVENT
config ARCH_MESON
bool "Amlogic Meson"
select MACH_IMX
select OF_CONTROL
select ENABLE_ARM_SOC_BOOT0_HOOK
+ imply DM_EVENT
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select DM
select SUPPORT_SPL
imply CMD_DM
+ imply DM_EVENT
config ARCH_IMX8ULP
bool "NXP i.MX8ULP platform"
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
imply CMD_DM
+ imply DM_EVENT
config ARCH_IMXRT
bool "NXP i.MXRT platform"
#include <cpu.h>
#include <cpu_func.h>
#include <dm.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/cache.h>
return 0;
}
-int arch_cpu_init_dm(void)
+static int imx8_init_mu(void *ctx, struct event *event)
{
struct udevice *devp;
int node, ret;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
int print_bootinfo(void)
{
#include <common.h>
#include <cpu_func.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/arch/imx-regs.h>
writew(enable, &wdog3->wmcr);
}
-int arch_cpu_init_dm(void)
+static int imx8m_check_clock(void *ctx, struct event *event)
{
struct udevice *dev;
int ret;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
int arch_cpu_init(void)
{
#include <asm/mach-imx/boot_mode.h>
#include <asm/global_data.h>
#include <efi_loader.h>
+#include <event.h>
#include <spl.h>
#include <asm/arch/rdc.h>
#include <asm/arch/s400_api.h>
return 0;
}
-int arch_cpu_init_dm(void)
+static int imx8ulp_check_mu(void *ctx, struct event *event)
{
struct udevice *devp;
int node, ret;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu);
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
#include <dm.h>
#include <debug_uart.h>
#include <errno.h>
+#include <event.h>
#include <init.h>
#include <net.h>
#include <ns16550.h>
#endif
-int arch_cpu_init_dm(void)
+static int am33xx_dm_post_init(void *ctx, struct event *event)
{
hw_data_init();
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#endif
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init);
*/
#include <common.h>
#include <debug_uart.h>
+#include <event.h>
#include <fdtdec.h>
#include <init.h>
#include <spl.h>
}
#endif
-int arch_cpu_init_dm(void)
+static int omap2_system_init(void *ctx, struct event *event)
{
early_system_init();
+
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init);
/*
* Routine: wait_for_command_complete
config TARGET_BOSTON
bool "Support Boston"
select DM
+ imply DM_EVENT
select DM_SERIAL
select MIPS_CM
select SYS_CACHE_SHIFT_6
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <event.h>
#include <init.h>
#include <malloc.h>
#include <asm/global_data.h>
}
/* arch specific CPU init after DM */
-int arch_cpu_init_dm(void)
+static int pic32_flash_prefetch(void *ctx, struct event *event)
{
/* flash prefetch */
prefetch_init();
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch);
/* Un-gate DDR2 modules (gated by default) */
static void ddr2_pmd_ungate(void)
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
+#include <event.h>
#include <init.h>
#include <irq_func.h>
#include <asm/cache.h>
}
#endif
-int arch_cpu_init_dm(void)
+static int nios_cpu_setup(void *ctx, struct event *event)
{
struct udevice *dev;
int ret;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup);
static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
int size)
#include <cpu.h>
#include <dm.h>
#include <dm/lists.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/encoding.h>
+#include <asm/system.h>
#include <dm/uclass-internal.h>
#include <linux/bitops.h>
}
#endif
-int arch_cpu_init_dm(void)
+int riscv_cpu_setup(void *ctx, struct event *event)
{
int ret;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup);
int arch_early_init_r(void)
{
#ifndef __ASM_RISCV_SYSTEM_H
#define __ASM_RISCV_SYSTEM_H
+struct event;
+
/*
* Interrupt configuring macros.
*
*
*/
+/* Hook to set up the CPU (called from SPL too) */
+int riscv_cpu_setup(void *ctx, struct event *event);
+
#endif /* __ASM_RISCV_SYSTEM_H */
#include <spl.h>
#include <asm/global_data.h>
#include <asm/smp.h>
+#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
if (ret)
panic("spl_early_init() failed: %d\n", ret);
- arch_cpu_init_dm();
+ riscv_cpu_setup(NULL, NULL);
preloader_console_init();
#include <common.h>
#include <cpu.h>
#include <dm.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <pci.h>
* Configure the internal clock of both SIO HS-UARTs, if they are enabled
* via FSP
*/
-int arch_cpu_init_dm(void)
+static int baytrail_uart_init(void *ctx, struct event *event)
{
struct udevice *dev;
void *base;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init);
static void set_max_freq(void)
{
#include <common.h>
#include <dm.h>
#include <cpu.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/cpu.h>
#include <asm/arch/pch.h>
#include <asm/arch/rcb.h>
-int arch_cpu_init_dm(void)
+static int broadwell_init_cpu(void *ctx, struct event *event)
{
struct udevice *dev;
int ret;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);
void set_max_freq(void)
{
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
+#include <event.h>
#include <fdtdec.h>
#include <init.h>
#include <log.h>
return x86_cpu_init_f();
}
-int arch_cpu_init_dm(void)
+static int ivybridge_cpu_init(void *ctx, struct event *ev)
{
struct pci_controller *hose;
struct udevice *bus, *dev;
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init);
#define PCH_EHCI0_TEMP_BAR0 0xe8000000
#define PCH_EHCI1_TEMP_BAR0 0xe8000400
#include <common.h>
#include <cpu_func.h>
+#include <event.h>
#include <init.h>
#include <mmc.h>
#include <asm/cache.h>
return 0;
}
-int arch_cpu_init_dm(void)
+static int quark_init_pcie(void *ctx, struct event *event)
{
/*
* Initialize PCIe controller
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie);
int checkcpu(void)
{
typedef asmlinkage int (*fsp_silicon_init_func)(struct fsps_upd *params);
+/**
+ * fsp_setup_pinctrl() - Set up the pinctrl for FSP
+ *
+ * @ctx: Event context (not used)
+ * @event: Event information (not used)
+ */
+int fsp_setup_pinctrl(void *ctx, struct event *event);
+
#endif
#include <bootstage.h>
#include <cbfs.h>
#include <dm.h>
+#include <event.h>
#include <init.h>
#include <log.h>
#include <spi.h>
#include <dm/uclass-internal.h>
#include <asm/fsp2/fsp_internal.h>
-int arch_cpu_init_dm(void)
+int fsp_setup_pinctrl(void *ctx, struct event *event)
{
struct udevice *dev;
ofnode node;
return ret;
}
+EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl);
#if !defined(CONFIG_TPL_BUILD)
binman_sym_declare(ulong, intel_fsp_m, image_pos);
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
+#include <asm/fsp2/fsp_api.h>
#include <asm/global_data.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
DECLARE_GLOBAL_DATA_PTR;
-__weak int arch_cpu_init_dm(void)
+__weak int fsp_setup_pinctrl(void *ctx, struct event *event)
{
return 0;
}
return ret;
}
#ifndef CONFIG_TPL
- ret = arch_cpu_init_dm();
+ ret = fsp_setup_pinctrl(NULL, NULL);
if (ret) {
debug("%s: arch_cpu_init_dm() failed\n", __func__);
return ret;
DECLARE_GLOBAL_DATA_PTR;
-__weak int arch_cpu_init_dm(void)
-{
- return 0;
-}
-
static int x86_tpl_init(void)
{
int ret;
debug("%s: arch_cpu_init() failed\n", __func__);
return ret;
}
- ret = arch_cpu_init_dm();
- if (ret) {
- debug("%s: arch_cpu_init_dm() failed\n", __func__);
- return ret;
- }
preloader_console_init();
return 0;
return 0;
}
-__weak int arch_cpu_init_dm(void)
-{
- return 0;
-}
-
__weak int checkcpu(void)
{
return 0;
arch_cpu_init, /* basic arch cpu dependent setup */
mach_cpu_init, /* SoC/machine dependent CPU setup */
initf_dm,
- arch_cpu_init_dm,
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
#endif
"test",
/* Events related to driver model */
+ "dm_post_init",
"dm_pre_probe",
"dm_post_probe",
"dm_pre_remove",
return ret;
}
}
+ if (CONFIG_IS_ENABLED(DM_EVENT)) {
+ ret = event_notify_null(EVT_DM_POST_INIT);
+ if (ret)
+ return log_msg_ret("ev", ret);
+ }
return 0;
}
EVT_TEST,
/* Events related to driver model */
+ EVT_DM_POST_INIT,
EVT_DM_PRE_PROBE,
EVT_DM_POST_PROBE,
EVT_DM_PRE_REMOVE,
*/
int arch_cpu_init(void);
-/**
- * arch_cpu_init_dm() - init CPU after driver model is available
- *
- * This is called immediately after driver model is available before
- * relocation. This is similar to arch_cpu_init() but is able to reference
- * devices
- *
- * Return: 0 if OK, -ve on error
- */
-int arch_cpu_init_dm(void);
-
/**
* mach_cpu_init() - SoC/machine dependent CPU setup
*