}
static int get_phyreg(struct eth_device *dev, unsigned char addr,
- unsigned char reg, unsigned short *value)
+ unsigned char reg, unsigned short *value)
{
int cmd;
int timeout = 50;
}
static int set_phyreg(struct eth_device *dev, unsigned char addr,
- unsigned char reg, unsigned short value)
+ unsigned char reg, unsigned short value)
{
int cmd;
int timeout = 50;
* Do this by checking model value field from ID2 register.
*/
static struct eth_device* verify_phyaddr(const char *devname,
- unsigned char addr)
+ unsigned char addr)
{
struct eth_device *dev;
unsigned short value;
iobase);
pci_write_config_dword(devno,
- PCI_COMMAND,
+ PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled. */
cfg_cmd->link = cpu_to_le32 (phys_to_bus((u32)&tx_ring[tx_next]));
memcpy(cfg_cmd->params, i82558_config_cmd,
- sizeof(i82558_config_cmd));
+ sizeof(i82558_config_cmd));
if (!wait_for_eepro100(dev)) {
printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
if (!(le16_to_cpu(tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
printf("TX error status = 0x%08X\n",
- le16_to_cpu(tx_ring[tx_cur].status));
+ le16_to_cpu(tx_ring[tx_cur].status));
goto Done;
}
i++) {
if (i >= TOUT_LOOP) {
printf("%s: Tx error buffer not ready\n",
- dev->name);
+ dev->name);
goto Done;
}
}
if (!(le16_to_cpu(tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
printf("TX error status = 0x%08X\n",
- le16_to_cpu(tx_ring[tx_cur].status));
+ le16_to_cpu(tx_ring[tx_cur].status));
goto Done;
}
if (!wait_for_eepro100(dev)) {
printf("%s: Tx error ethernet controller not ready.\n",
- dev->name);
+ dev->name);
goto Done;
}
if (!(le16_to_cpu(tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
printf("TX error status = 0x%08X\n",
- le16_to_cpu(tx_ring[tx_cur].status));
+ le16_to_cpu(tx_ring[tx_cur].status));
goto Done;
}