Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
immr->sysconf.spcr |= 0x00400000;
}
-
/*
* Handle external interrupts
*/
{
}
-
/*
* Install and free an interrupt handler.
*/
{
}
-
void irq_free_handler(int irq)
{
}
-
void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}
-
#if defined(CONFIG_CMD_IRQ)
/* ripped this out of ppc4xx/interrupts.c */
}
}
-
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
panic("Software Emulation Exception");
}
-
void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
return 0;
}
-
/* ------------------------------------------------------------------------- */
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
return 1;
}
-
/*
* Get timebase clock frequency
*/
return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
}
-
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
}
#endif
-
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
ft_fixup_l2cache(blob);
}
-
void fdt_add_enet_stashing(void *fdt)
{
do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
printf("SERDES: timeout resetting bank %u\n", bank + 1);
}
-
static void __soc_serdes_init(void)
{
/* Allow for SoC-specific initialization in <SOC>_serdes.c */
struct law_entry e;
#endif
-
/* use last 4K of mapped memory */
bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ?
CFG_MAX_MEM_MAPPED : gd->ram_size) +
[0x03] = {PCIE1, PCIE2},
};
-
int is_serdes_configured(enum srds_prtcl device)
{
int ret;
else return (1);
}
-
/********************************************
* get_bus_freq
* return system bus freq in Hz
#include <asm/processor.h>
#include <asm/io.h>
-
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
#include <asm/io.h>
#include <asm/ppc.h>
-
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
PCIE2, PCIE2, PCIE2, PCIE2},
clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
-
#endif /* not SPL */
}
}
-
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
if (pin > 31)
rcode = 1;
-
switch (argv[3][0]) {
case 'd':
if (argv[3][1] == 'a')
}
}
-
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
panic("Software Emulation Exception");
}
-
void UnknownException(struct pt_regs *regs)
{
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
return cpu->num_cores;
}
-
/*
* Check if the given core ID is valid
*
void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
#endif
-
void print_lbc_regs(void)
{
int i;
return __ilog2_u64(val) + 1;
}
-
static inline int count_lsb_zeroes(unsigned long val)
{
return ffs(val) - 1;
u32 i = 0;
u32 base_addr = CFG_SYS_PAMU_ADDR;
-
for (i = 0; i < CFG_NUM_PAMU; i++) {
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
sync();
}
}
-
static uint64_t find_max(uint64_t arr[], int num)
{
int i = 0;
#define LAWBAR_SHIFT 12
#endif
-
static inline phys_addr_t get_law_base_addr(int idx)
{
#ifdef CONFIG_FSL_CORENET
return result + ffz(tmp);
}
-
#define _EXT2_HAVE_ASM_BITOPS_
#ifdef __KERNEL__
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
-
#elif defined(CONFIG_ARCH_C29X)
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#error FT_FSL_PCI_SETUP not defined
#endif
-
#endif
#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
-
#define IO_SPACE_LIMIT ~0
#define memset_io(a,b,c) memset((void __force *)(a),(b),(c))
#define PT_MASK 0x02FF
#define PG_SHIFT (12) /* Page Entry */
-
/* MMU context */
typedef struct _MMU_context {
#define M_CASID 793 /* Address space ID (context) to match */
#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
-
/* These are the Ks and Kp from the PowerPC books. For proper operation,
* Ks = 0, Kp = 1.
*/
#define MD_SVALID 0x00000001 /* Segment entry is valid */
/* Reset value is undefined */
-
/* Real page number. Defined by the pte. Writing this register
* causes a TLB entry to be created for the data TLB, using
* additional information from the MD_EPN, and MD_TWC registers.
#ifndef _PPC_KERNEL_MPC8349_PCI_H
#define _PPC_KERNEL_MPC8349_PCI_H
-
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
#define M8265_PCIMSK0 0x101c4
#define PCIMSK_512MB 0xE0000000
#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
-
#define M826X_SCCR_PCI_MODE_EN 0x100
-
/*
* Outbound ATU registers (3 sets). These registers control how 60x bus
* (local) addresses are translated to PCI addresses when the MPC826x is
#include <asm/ptrace.h>
-
struct sigcontext_struct {
unsigned long _unused[4];
int signal;
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-
#include <config.h>
#include <bootm.h>
#include <bootstage.h>
return val;
}
-
static __inline__ void set_dec (unsigned long val)
{
if (val)
projects / u-boot.git / commitdiff
