]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
riscv: dts: sophgo: Add ethernet node
authorKongyang Liu <seashell11234455@gmail.com>
Sat, 20 Apr 2024 07:00:28 +0000 (15:00 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 1 May 2024 16:01:18 +0000 (00:01 +0800)
Add ethernet node for cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/dts/cv1800b-milkv-duo.dts
arch/riscv/dts/cv18xx.dtsi

index 94e64ddce8fa3f878d72750adc011c1c9e0f81d4..f6ae8828f37a7eee194c62b59fa70b609dc1c11a 100644 (file)
        };
 };
 
+&ethernet0 {
+       status = "okay";
+       phy-mode = "rmii";
+};
+
 &osc {
        clock-frequency = <25000000>;
 };
index ec99c4deeb69e5061da01d74fc9e7cdc15376c43..5e83ee18539c3b60e4b787e16314668179f3ebf0 100644 (file)
                #clock-cells = <0>;
        };
 
+       eth_csrclk: eth-csrclk {
+               compatible = "fixed-clock";
+               clock-frequency = <250000000>;
+               clock-output-names = "eth_csrclk";
+               #clock-cells = <0x0>;
+       };
+
+       eth_ptpclk: eth-ptpclk {
+               compatible = "fixed-clock";
+               clock-frequency = <50000000>;
+               clock-output-names = "eth_ptpclk";
+               #clock-cells = <0x0>;
+       };
+
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&plic>;
                        };
                };
 
+               ethernet0: ethernet@4070000 {
+                       compatible = "sophgo,cv1800b-dwmac";
+                       reg = <0x04070000 0x10000>;
+                       interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&eth_csrclk>, <&eth_ptpclk>;
+                       clock-names = "stmmaceth", "ptp_ref";
+                       status = "disabled";
+               };
+
                uart0: serial@4140000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x04140000 0x100>;