armv8: dts: ls1046a: Add the PCIe EP node

Add the PCIe EP node for ls1046a.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 8673a5db2af8ebc6c4b7467137bf88bf9e1af4c4..3f11d6cd18dcb247c65751e0c0b9eb07e9d4deb5 100644 (file)
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -257,6 +257,17 @@
                                  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                };
 
+               pcie_ep@3400000 {
+                       compatible = "fsl,ls-pcie-ep";
+                       reg = <0x00 0x03400000 0x0 0x80000
+                              0x00 0x034c0000 0x0 0x40000
+                              0x40 0x00000000 0x8 0x00000000>;
+                       reg-names = "regs", "ctrl", "addr_space";
+                       num-ib-windows = <6>;
+                       num-ob-windows = <8>;
+                       big-endian;
+               };
+
                pcie@3500000 {
                        compatible = "fsl,ls-pcie", "snps,dw-pcie";
                        reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
@@ -274,6 +285,17 @@
                                  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                };
 
+               pcie_ep@3500000 {
+                       compatible = "fsl,ls-pcie-ep";
+                       reg = <0x00 0x03500000 0x0 0x80000
+                              0x00 0x035c0000 0x0 0x40000
+                              0x48 0x00000000 0x8 0x00000000>;
+                       reg-names = "regs", "ctrl", "addr_space";
+                       num-ib-windows = <6>;
+                       num-ob-windows = <8>;
+                       big-endian;
+               };
+
                pcie@3600000 {
                        compatible = "fsl,ls-pcie", "snps,dw-pcie";
                        reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
@@ -290,6 +312,17 @@
                                  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                };
 
+               pcie_ep@3600000 {
+                       compatible = "fsl,ls-pcie-ep";
+                       reg = <0x00 0x03600000 0x0 0x80000
+                              0x00 0x036c0000 0x0 0x40000
+                              0x50 0x00000000 0x8 0x00000000>;
+                       reg-names = "regs", "ctrl", "addr_space";
+                       num-ib-windows = <6>;
+                       num-ob-windows = <8>;
+                       big-endian;
+               };
+
                sata: sata@3200000 {
                        compatible = "fsl,ls1046a-ahci";
                        reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */