arm: dts: socfpga: stratix10: Add freeze controller node

The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index 61df425f14b1de36dfb28a81e755f8ce1fc0cd2d..75a29045da380f1f9e8b28f12e109888952537f4 100755 (executable)
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -2,7 +2,7 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
  */
 
 #include "socfpga_stratix10-u-boot.dtsi"
@@ -10,6 +10,15 @@
 /{
        aliases {
                spi0 = &qspi;
+               freeze_br0 = &freeze_controller;
+       };
+
+       soc {
+               freeze_controller: freeze_controller@f9000450 {
+                       compatible = "altr,freeze-bridge-controller";
+                       reg = <0xf9000450 0x00000010>;
+                       status = "disabled";
+               };
        };
 };