powerpc/85xx: add T4080 SoC support

The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 409478539ec1a7eb16750f19baa0635faed2e51b..ad26b432f1832ea356907c7bf0923dd23dec0abb 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o
 obj-$(CONFIG_PPC_P5040) += p5040_ids.o
 obj-$(CONFIG_PPC_T4240) += t4240_ids.o
 obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_T4080) += t4240_ids.o
 obj-$(CONFIG_PPC_B4420) += b4860_ids.o
 obj-$(CONFIG_PPC_B4860) += b4860_ids.o
 obj-$(CONFIG_PPC_T1040) += t1040_ids.o
@@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
 obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
 obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
 obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
 obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
 obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
 obj-$(CONFIG_BSC9132) += bsc9132_serdes.o

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 12e8e10d483cacc7493c55b24f57fce2f88240cd..684d4007e48a9f9be845c12f533fc9a0d0b873ef 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -77,6 +77,30 @@ int checkcpu (void)
        major = SVR_MAJ(svr);
        minor = SVR_MIN(svr);
 
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+       if (SVR_SOC_VER(svr) == SVR_T4080) {
+               ccsr_rcpm_t *rcpm =
+                       (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+               setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+                            FSL_CORENET_DEVDISR2_DTSEC1_9);
+               setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+               setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+               /* It needs SW to disable core4~7 as HW design sake on T4080 */
+               for (i = 4; i < 8; i++)
+                       cpu_disable(i);
+
+               /* request core4~7 into PH20 state, prior to entering PCL10
+                * state, all cores in cluster should be placed in PH20 state.
+                */
+               setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+               /* put the 2nd cluster into PCL10 state */
+               setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+       }
+#endif
+
        if (cpu_numcores() > 1) {
 #ifndef CONFIG_MP
                puts("Unicore software on multiprocessor system!!\n"

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 36ef23232ed044db5cf3316067b445d213c0f87a..7e2746412bd219ec5eeca1d2789abdfdfc1af01d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -462,10 +462,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 int enable_cluster_l2(void)
 {
        int i = 0;
-       u32 cluster;
+       u32 cluster, svr = get_svr();
        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        struct ccsr_cluster_l2 __iomem *l2cache;
 
+       /* only the L2 of first cluster should be enabled as expected on T4080,
+        * but there is no EOC in the first cluster as HW sake, so return here
+        * to skip enabling L2 cache of the 2nd cluster.
+        */
+       if (SVR_SOC_VER(svr) == SVR_T4080)
+               return 0;
+
        cluster = in_be32(&gur->tp_cluster[i].lower);
        if (cluster & TP_CLUSTER_EOC)
                return 0;

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d516d4e4a627aa669281824815db01defb3c97d6..3236f6a5da6b577af94441996a89127e1ddeac81 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info)
         * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
         * it uses 6.
         */
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
        if (SVR_MAJ(get_svr()) >= 2)
                mem_pll_rat *= 2;
 #endif

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index ff55e3c357c3371b9f078d3da40550b3710a7cd4..1f99a0a8978f11d847ea59318220d88453a4cec1 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
        {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
        {}
 };
-#elif defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 static const struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
        {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 35795c4fbe7a12896c7afad150c1986414bfad55..dfedc536ffb902144867dd113fe4eb36500ab2e0 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -62,6 +62,7 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(T4240, T4240, 0),
        CPU_TYPE_ENTRY(T4120, T4120, 0),
        CPU_TYPE_ENTRY(T4160, T4160, 0),
+       CPU_TYPE_ENTRY(T4080, T4080, 4),
        CPU_TYPE_ENTRY(B4860, B4860, 0),
        CPU_TYPE_ENTRY(G4860, G4860, 0),
        CPU_TYPE_ENTRY(G4060, G4060, 0),

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 0d6eb491f1af565aa5322be40f231245575f2b80..8a7d4d8a1dc747165e3d1126e767279df5c4824b 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -595,7 +595,8 @@
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
@@ -611,13 +612,18 @@
 #define CONFIG_SYS_NUM_FM2_10GEC       2
 #define CONFIG_NUM_DDR_CONTROLLERS     3
 #else
-#define CONFIG_MAX_CPUS                        8
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1 }
-#define CONFIG_SYS_NUM_FM1_DTSEC       7
+#define CONFIG_SYS_NUM_FM1_DTSEC       6
 #define CONFIG_SYS_NUM_FM1_10GEC       1
-#define CONFIG_SYS_NUM_FM2_DTSEC       7
+#define CONFIG_SYS_NUM_FM2_DTSEC       8
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
+#if defined(CONFIG_PPC_T4160)
+#define CONFIG_MAX_CPUS                        8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1 }
+#elif defined(CONFIG_PPC_T4080)
+#define CONFIG_MAX_CPUS                        4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1 }
+#endif
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     5
 #define CONFIG_SYS_FSL_NUM_LAWS                32

diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index d820121ee3a1d802ccc5b6e7a5cc23b679d0cc9b..64da4bb3bae185ae180908332f5033b2b2b701ea 100644 (file)
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -16,6 +16,7 @@ static inline bool has_erratum_a006379(void)
        u32 svr = get_svr();
        if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
            ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+           ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
            ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
            ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
            ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
@@ -49,6 +50,7 @@ static inline bool has_erratum_a006261(void)
                return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
        case SVR_T4240:
        case SVR_T4160:
+       case SVR_T4080:
                return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
        case SVR_T1040:
                return IS_SVR_REV(svr, 1, 0);

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 741b8618d11fbd25ffd99e6658b95e122f5e72cf..eff573b5aded3c83b75dc83083aa46bc60897b98 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1748,7 +1748,8 @@ typedef struct ccsr_gur {
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT      8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00fe0000
@@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 72f30feee6260c514e1c662f8f65eee38d385dbb..a6f121e113a617f75a65dd683a5aae18f848d2ad 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1111,6 +1111,7 @@
 #define SVR_T4240      0x824000
 #define SVR_T4120      0x824001
 #define SVR_T4160      0x824100
+#define SVR_T4080      0x824102
 #define SVR_C291       0x850000
 #define SVR_C292       0x850020
 #define SVR_C293       0x850030

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index ee5d768937766f8b8dc012896f36ff87b01f22ae..5ae3b167a93d681fed0b929972966da805174328 100644 (file)
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o
 obj-$(CONFIG_PPC_T2081) += t2080.o
 obj-$(CONFIG_PPC_T4240) += t4240.o
 obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o