# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
# CONFIG_ISO_PARTITION is not set
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
+CONFIG_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
}
+#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY)
+static int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+ u32 sdram_size = gd->ram_size;
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ phys_addr_t cpu;
+ dma_addr_t bus;
+ u64 dma_size;
+ int ret;
+
+ ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size);
+ if (ret) {
+ dev_err(dev, "failed to get dma address\n");
+ return ret;
+ }
+
+ uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align);
+ return 0;
+}
+#else
+static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+ /* Delegate framebuffer allocation to video-uclass */
+ return 0;
+}
+#endif
+
static int stm32_ltdc_probe(struct udevice *dev)
{
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
priv->crop_h = timings.vactive.typ;
priv->alpha = 0xFF;
+ ret = stm32_ltdc_alloc_fb(dev);
+ if (ret)
+ return ret;
+
dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
timings.hactive.typ, timings.vactive.typ,
VNBITS(priv->l2bpp), uc_plat->base);