]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: imx8mm-cl-iot-gate: Enable DM_SERIAL
authorPeng Fan <peng.fan@nxp.com>
Sat, 11 Jun 2022 12:20:56 +0000 (20:20 +0800)
committerStefano Babic <sbabic@denx.de>
Tue, 14 Jun 2022 19:33:13 +0000 (21:33 +0200)
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
board/compulab/imx8mm-cl-iot-gate/spl.c
configs/imx8mm-cl-iot-gate-optee_defconfig
configs/imx8mm-cl-iot-gate_defconfig
include/configs/imx8mm-cl-iot-gate.h

index 2dc62d6682e041e1f96fbceeaf6262d808fbf5c6..f183704c9d2f3be74e6a76115a30677474fe2721 100644 (file)
@@ -83,14 +83,8 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
-static iomux_v3_cfg_t const uart_pads[] = {
-       IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const wdog_pads[] = {
        IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@@ -103,8 +97,6 @@ int board_early_init_f(void)
 
        set_wdog_reset(wdog);
 
-       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
        return 0;
 }
 
@@ -155,8 +147,6 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
-       preloader_console_init();
-
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -166,6 +156,8 @@ void board_init_f(ulong dummy)
                hang();
        }
 
+       preloader_console_init();
+
        ret = uclass_get_device_by_name(UCLASS_CLK,
                                        "clock-controller@30380000",
                                        &dev);
index 57ecd7bb3b69b44020621dce70e8f0ff8aa21c1a..8005591209601aea18aa2ba27bce1e88664f7d28 100644 (file)
@@ -121,6 +121,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_ABX80X=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index 67f7576f996b578c85d3fd031fff2e6d47c4bc88..dae7ddc20e07192e5e67b386519f2d038f1f04ad 100644 (file)
@@ -124,6 +124,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_ABX80X=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index 297d56b427f86d520a0046856cd2b6797f2c257a..fc738ed410e2a71e2cfad0bd8ed6fd55824cd743 100644 (file)
 #define PHYS_SDRAM                     0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(3)
-
 /* USDHC */
 
 #define CONFIG_SYS_FSL_USDHC_NUM       2