}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2