andes: Unify naming policy for Andes related source

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e20ef63bba016b2f7c3a7b14aff0c5ea1b4b1a4..fa3b016c52728862019c426f031262c40901ee51 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -80,7 +80,7 @@ config SPL_ZERO_MEM_BEFORE_USE
          Sifive core devices that uses L2 cache to store SPL.
 
 # board-specific options below
-source "board/AndesTech/ae350/Kconfig"
+source "board/andestech/ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
@@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig"
 source "board/xilinx/mbv/Kconfig"
 
 # platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
 source "arch/riscv/cpu/cv1800b/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"

diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig
similarity index 91%
rename from arch/riscv/cpu/andesv5/Kconfig
rename to arch/riscv/cpu/andes/Kconfig
index e3efb0de8f05f91e044a67df032012b1373506b5..120fec5e5409b6e31b251fa9d3a7c546ac2cfcfe 100644 (file)
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -1,4 +1,4 @@
-config RISCV_NDS
+config RISCV_ANDES
        bool
        select ARCH_EARLY_INIT_R
        select SYS_CACHE_SHIFT_6
@@ -8,7 +8,7 @@ config RISCV_NDS
        imply ANDES_PLMT_TIMER
        imply SPL_ANDES_PLMT_TIMER
        imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
-       imply V5L2_CACHE
+       imply ANDES_L2_CACHE
        imply SPL_CPU
        imply SPL_OPENSBI
        imply SPL_LOAD_FIT

diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile
similarity index 100%
rename from arch/riscv/cpu/andesv5/Makefile
rename to arch/riscv/cpu/andes/Makefile

diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c
similarity index 90%
rename from arch/riscv/cpu/andesv5/cache.c
rename to arch/riscv/cpu/andes/cache.c
index 269bb27f75a642bb14f3f54f0c56d245f4ee1f09..7d3df8722dd0e1d9e63eced941a2bd48d7e2feee 100644 (file)
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -12,21 +12,21 @@
 #include <dm/uclass-internal.h>
 #include <asm/arch-andes/csr.h>
 
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
 void enable_caches(void)
 {
        struct udevice *dev;
        int ret;
 
        ret = uclass_get_device_by_driver(UCLASS_CACHE,
-                                         DM_DRIVER_GET(v5l2_cache),
+                                         DM_DRIVER_GET(andes_l2_cache),
                                          &dev);
        if (ret) {
-               log_debug("Cannot enable v5l2 cache\n");
+               log_debug("Cannot enable Andes L2 cache\n");
        } else {
                ret = cache_enable(dev);
                if (ret)
-                       log_debug("v5l2 cache enable failed\n");
+                       log_debug("Failed to enable Andes L2 cache\n");
        }
 }
 
@@ -78,7 +78,7 @@ void dcache_enable(void)
        asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
 #endif
 
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
        cache_ops(cache_enable);
 #endif
 }
@@ -89,7 +89,7 @@ void dcache_disable(void)
        asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
 #endif
 
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
        cache_ops(cache_disable);
 #endif
 }

diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andes/cpu.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/cpu.c
rename to arch/riscv/cpu/andes/cpu.c

diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andes/spl.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/spl.c
rename to arch/riscv/cpu/andes/spl.c

diff --git a/board/AndesTech/ae350/Kconfig b/board/andestech/ae350/Kconfig
similarity index 91%
rename from board/AndesTech/ae350/Kconfig
rename to board/andestech/ae350/Kconfig
index a85e7d6351702861cb84ba0ff5687017adb7b197..096564b3dc166a873fc49fb30eef48d09793c6d0 100644 (file)
--- a/board/AndesTech/ae350/Kconfig
+++ b/board/andestech/ae350/Kconfig
@@ -1,13 +1,13 @@
 if TARGET_ANDES_AE350
 
 config SYS_CPU
-       default "andesv5"
+       default "andes"
 
 config SYS_BOARD
        default "ae350"
 
 config SYS_VENDOR
-       default "AndesTech"
+       default "andestech"
 
 config SYS_SOC
        default "ae350"
@@ -33,7 +33,7 @@ config SYS_FDT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
-       select RISCV_NDS
+       select RISCV_ANDES
        select SUPPORT_SPL
        select BINMAN if SPL
        imply SMP

diff --git a/board/AndesTech/ae350/MAINTAINERS b/board/andestech/ae350/MAINTAINERS
similarity index 95%
rename from board/AndesTech/ae350/MAINTAINERS
rename to board/andestech/ae350/MAINTAINERS
index a6bc90baf883c0865682b0c837c56b3a4f09fb98..31e34e610dff6f9700125542375512f2d20c5498 100644 (file)
--- a/board/AndesTech/ae350/MAINTAINERS
+++ b/board/andestech/ae350/MAINTAINERS
@@ -1,7 +1,7 @@
 AE350 BOARD
 M:     Rick Chen <rick@andestech.com>
 S:     Maintained
-F:     board/AndesTech/ae350/
+F:     board/andestech/ae350/
 F:     include/configs/ae350.h
 F:     configs/ae350_rv32_defconfig
 F:     configs/ae350_rv32_falcon_defconfig

diff --git a/board/AndesTech/ae350/Makefile b/board/andestech/ae350/Makefile
similarity index 100%
rename from board/AndesTech/ae350/Makefile
rename to board/andestech/ae350/Makefile

diff --git a/board/AndesTech/ae350/ae350.c b/board/andestech/ae350/ae350.c
similarity index 99%
rename from board/AndesTech/ae350/ae350.c
rename to board/andestech/ae350/ae350.c
index 62b93b4ecba12d07bf8a2f77683d0bac9285744e..5ae5baed6ba2e57a470448f40e75f0210aa14a37 100644 (file)
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/andestech/ae350/ae350.c
@@ -99,7 +99,7 @@ void *board_fdt_blob_setup(int *err)
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init()
 {
-       /* enable v5l2 cache */
+       /* enable andes-l2 cache */
        if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
                enable_caches();
 }

diff --git a/doc/board/AndesTech/adp-ag101p.rst b/doc/board/andestech/adp-ag101p.rst
similarity index 100%
rename from doc/board/AndesTech/adp-ag101p.rst
rename to doc/board/andestech/adp-ag101p.rst

diff --git a/doc/board/AndesTech/ae350.rst b/doc/board/andestech/ae350.rst
similarity index 100%
rename from doc/board/AndesTech/ae350.rst
rename to doc/board/andestech/ae350.rst

diff --git a/doc/board/AndesTech/index.rst b/doc/board/andestech/index.rst
similarity index 100%
rename from doc/board/AndesTech/index.rst
rename to doc/board/andestech/index.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 428faa810bec4ee78e4349eeebfcabaf94e0b30d..2340eeb07778b10bb1af01d7a3292e846c9c08d4 100644 (file)
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -8,7 +8,7 @@ Board-specific doc
 
    actions/index
    advantech/index
-   AndesTech/index
+   andestech/index
    allwinner/index
    amlogic/index
    anbernic/index

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 26c2d80a1c568dece31fa9d8e6ac5520469a92c9..4f35865744458cb0b243e204d2ad71de71be643e 100644 (file)
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,11 +22,11 @@ config L2X0_CACHE
          ARMv7(32-bit) devices. The driver configures the cache settings
          found in the device tree.
 
-config V5L2_CACHE
-       bool "Andes V5L2 cache driver"
+config ANDES_L2_CACHE
+       bool "Andes L2 cache driver"
        select CACHE
        help
-         Support Andes V5L2 cache controller in AE350 platform.
+         Support Andes L2 cache controller in AE350 platform.
          It will configure tag and data ram timing control from the
          device tree and enable L2 cache.
 

diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 78e673d09e5b52f698da1efbe335aebbf1b279b5..e1b71e0ed514e693341b547fbbc387904ae279fc 100644 (file)
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -3,6 +3,6 @@ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
-obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o
 obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
 obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o

diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-andes-l2.c
similarity index 84%
rename from drivers/cache/cache-v5l2.c
rename to drivers/cache/cache-andes-l2.c
index f0b8ecc88079e23b0ad2de4fa84f20aae0e93830..7de8f16852dc61676d2d756a6af76db7d9535269 100644 (file)
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-andes-l2.c
@@ -72,7 +72,7 @@ static u32 status_bit_offset = 0x4;
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct v5l2_plat {
+struct andes_l2_plat {
        struct l2cache  *regs;
        u32             iprefetch;
        u32             dprefetch;
@@ -80,9 +80,9 @@ struct v5l2_plat {
        u32             dram_ctl[2];
 };
 
-static int v5l2_enable(struct udevice *dev)
+static int andes_l2_enable(struct udevice *dev)
 {
-       struct v5l2_plat *plat = dev_get_plat(dev);
+       struct andes_l2_plat *plat = dev_get_plat(dev);
        volatile struct l2cache *regs = plat->regs;
 
        if (regs)
@@ -91,9 +91,9 @@ static int v5l2_enable(struct udevice *dev)
        return 0;
 }
 
-static int v5l2_disable(struct udevice *dev)
+static int andes_l2_disable(struct udevice *dev)
 {
-       struct v5l2_plat *plat = dev_get_plat(dev);
+       struct andes_l2_plat *plat = dev_get_plat(dev);
        volatile struct l2cache *regs = plat->regs;
        u8 hart = gd->arch.boot_hart;
        void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
@@ -113,9 +113,9 @@ static int v5l2_disable(struct udevice *dev)
        return 0;
 }
 
-static int v5l2_of_to_plat(struct udevice *dev)
+static int andes_l2_of_to_plat(struct udevice *dev)
 {
-       struct v5l2_plat *plat = dev_get_plat(dev);
+       struct andes_l2_plat *plat = dev_get_plat(dev);
        struct l2cache *regs;
 
        regs = dev_read_addr_ptr(dev);
@@ -137,9 +137,9 @@ static int v5l2_of_to_plat(struct udevice *dev)
        return 0;
 }
 
-static int v5l2_probe(struct udevice *dev)
+static int andes_l2_probe(struct udevice *dev)
 {
-       struct v5l2_plat *plat = dev_get_plat(dev);
+       struct andes_l2_plat *plat = dev_get_plat(dev);
        struct l2cache *regs = plat->regs;
        u32 cfg_val, ctl_val;
 
@@ -182,23 +182,23 @@ static int v5l2_probe(struct udevice *dev)
        return 0;
 }
 
-static const struct udevice_id v5l2_cache_ids[] = {
+static const struct udevice_id andes_l2_cache_ids[] = {
        { .compatible = "cache" },
        {}
 };
 
-static const struct cache_ops v5l2_cache_ops = {
-       .enable         = v5l2_enable,
-       .disable        = v5l2_disable,
+static const struct cache_ops andes_l2_cache_ops = {
+       .enable         = andes_l2_enable,
+       .disable        = andes_l2_disable,
 };
 
-U_BOOT_DRIVER(v5l2_cache) = {
-       .name   = "v5l2_cache",
+U_BOOT_DRIVER(andes_l2_cache) = {
+       .name   = "andes_l2_cache",
        .id     = UCLASS_CACHE,
-       .of_match = v5l2_cache_ids,
-       .of_to_plat = v5l2_of_to_plat,
-       .probe  = v5l2_probe,
-       .plat_auto      = sizeof(struct v5l2_plat),
-       .ops = &v5l2_cache_ops,
+       .of_match = andes_l2_cache_ids,
+       .of_to_plat = andes_l2_of_to_plat,
+       .probe  = andes_l2_probe,
+       .plat_auto      = sizeof(struct andes_l2_plat),
+       .ops = &andes_l2_cache_ops,
        .flags  = DM_FLAG_PRE_RELOC,
 };