CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_HSMMC2_8BIT=y
CONFIG_PALMAS_POWER=y
CONFIG_SCSI=y
CONFIG_SCSI_AHCI_PLAT=y
If unsure, say N.
+config HSMMC2_8BIT
+ bool "Enable 8-bit interface for eMMC (interface #2)"
+ depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \
+ AM43XX || ARCH_KEYSTONE)
+
config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
depends on ARCH_RMOBILE
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_HSMMC2_8BIT
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
#include <configs/ti_omap5_common.h>
-/* Enhance our eMMC support / experience. */
-#define CONFIG_HSMMC2_8BIT
-
/* CPSW Ethernet */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
* we don't need to do it twice.
*/
-#define CONFIG_HSMMC2_8BIT
-
#include <configs/ti_armv7_omap.h>
#define V_OSCK 24000000 /* Clock output from T2 */
#include <configs/ti_omap5_common.h>
-/* Enhance our eMMC support / experience. */
-#define CONFIG_HSMMC2_8BIT
-
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
/* MMC ENV related defines */
-/* Enhance our eMMC support / experience. */
-#define CONFIG_HSMMC2_8BIT
-
/* Required support for the TCA642X GPIO we have on the uEVM */
#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
#define CFG_SYS_I2C_TCA642X_ADDR 0x22