da850: modifications for Logic PD Rev.3 AM18xx EVM

AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 4a3af7d3b6ad8e389de7daf7b391e60e9f5d8710..692d50755ac2aa547c4f4ebb4dcb7b269159a2c5 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -159,6 +159,10 @@ typedef volatile unsigned int *    dv_reg_p;
 #define HOST1CFG                               (DAVINCI_BOOTCFG_BASE + 0x44)
 #define PSC0_MDCTL                             (DAVINCI_PSC0_BASE + 0xa00)
 
+#define GPIO_BANK0_REG_DIR_ADDR                        (DAVINCI_GPIO_BASE + 0x10)
+#define GPIO_BANK0_REG_OPDATA_ADDR             (DAVINCI_GPIO_BASE + 0x14)
+#define GPIO_BANK0_REG_SET_ADDR                        (DAVINCI_GPIO_BASE + 0x18)
+#define GPIO_BANK0_REG_CLR_ADDR                        (DAVINCI_GPIO_BASE + 0x1c)
 #define GPIO_BANK2_REG_DIR_ADDR                        (DAVINCI_GPIO_BASE + 0x38)
 #define GPIO_BANK2_REG_OPDATA_ADDR             (DAVINCI_GPIO_BASE + 0x3c)
 #define GPIO_BANK2_REG_SET_ADDR                        (DAVINCI_GPIO_BASE + 0x40)

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 8c3d64e787179e2c1ee53c61699b82a4b2d0ea68..2f950e7bdf686b62cfada003babf9a43d5dd6c47 100644 (file)
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -109,6 +109,8 @@ const struct pinmux_config nand_pins[] = {
 #elif defined(CONFIG_USE_NOR)
 /* NOR pin muxer settings */
 const struct pinmux_config nor_pins[] = {
+       /* GP0[11] is required for NOR to work on Rev 3 EVMs */
+       { pinmux(0), 8, 4 },    /* GP0[11] */
        { pinmux(5), 1, 6 },
        { pinmux(6), 1, 6 },
        { pinmux(7), 1, 0 },
@@ -278,6 +280,7 @@ u32 get_board_rev(void)
 
 int board_init(void)
 {
+       u32 val;
 #ifndef CONFIG_USE_IRQ
        irq_init();
 #endif
@@ -325,6 +328,16 @@ int board_init(void)
        if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
                return 1;
 
+#ifdef CONFIG_USE_NOR
+       /* Set the GPIO direction as output */
+       clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+       /* Set the output as low */
+       val = readl(GPIO_BANK0_REG_SET_ADDR);
+       val |= (0x01 << 11);
+       writel(val, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
 #ifdef CONFIG_DRIVER_TI_EMAC
        if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
                return 1;