return get_timer_masked ();
}
-void __udelay (unsigned long usec)
+void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
asm ("sync;isync");
- udelay (500);
+ udelay(500);
ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
asm ("sync; isync");
- udelay (500);
+ udelay(500);
ddr = &immap->im_ddr2;
ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
asm ("sync;isync");
- udelay (500);
+ udelay(500);
ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
asm ("sync; isync");
- udelay (500);
+ udelay(500);
#endif
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
/* delay for <count> ms... */
for (i=0; i<count; i++)
- udelay (1000);
+ udelay(1000);
/* check for ctrl-c to abort... */
if (ctrlc()) {
/* delay for <count> ms... */
for (i=0; i<count; i++)
- udelay (1000);
+ udelay(1000);
/* check for ctrl-c to abort... */
if (ctrlc()) {
port[num].ctl_reg = 0x08; /*Default value of control reg */
writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- udelay (10);
+ udelay(10);
writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
- udelay (10);
+ udelay(10);
writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
/* spec mandates ">= 2ms" before checking status.
cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
writeb (cmd, port[num].ioaddr.command_addr);
readb (port[num].ioaddr.altstatus_addr);
- udelay (10);
+ udelay(10);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
if (status & ATA_ERR) {
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
- udelay (50);
+ udelay(50);
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
if (readl (port) & VND_TF_CNST_INTST) {
break;
}
- udelay (1000);
+ udelay(1000);
max--;
} while ((max > 0));
if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
break;
}
- udelay (1000);
+ udelay(1000);
max--;
} while ((status & bits) && (max > 0));
int i;
for (i = 0; i < count; i++)
- udelay (1000);
+ udelay(1000);
}
/* Read up to 255 sectors
output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
readb (port[num].ioaddr.altstatus_addr);
- udelay (50);
+ udelay(50);
++n;
++blknr;
/* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
fns->config (0, 1, cookie);
- udelay (5); /* nCONFIG low pulse width 2usec */
+ udelay(5); /* nCONFIG low pulse width 2usec */
fns->config (1, 1, cookie);
- udelay (100); /* nCONFIG high to first rising edge on DCLK */
+ udelay(100); /* nCONFIG high to first rising edge on DCLK */
/* 3. Start the Data cycle with clk deasserted */
bytecount = 0;
/* 4. Set one last clock and check conf done signal */
fns->clk (1, 1, cookie);
- udelay (100);
+ udelay(100);
if (!fns->done (cookie)) {
printf (" error!.\n");
fns->abort (cookie);
/* Wait for the reset to complete, or time out (500 ms) */
while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
- udelay (1000);
+ udelay(1000);
if (--delay_cnt == 0) {
printf ("Failed to reset PHY!\n");
return -1;
if ((tmpval & txbs_txdp) == 0)
break;
- udelay (100);
+ udelay(100);
}
if (TimeOutCnt)
if (bmsr_val & BMSR_LSTATUS) {
break;
}
- udelay (100);
+ udelay(100);
}
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
if (bmsr_val & BMSR_ANEGCOMPLETE) {
break;
}
- udelay (100);
+ udelay(100);
}
} else
debug ("ax88180: Auto-negotiation is disabled.\n");
tmp_regval = INW (dev, PROMCTRL);
if ((tmp_regval & RELOAD_EEPROM) == 0)
break;
- udelay (1000);
+ udelay(1000);
}
/* Get MAC addresses */
*/
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
- udelay (10 * 1000);
+ udelay(10 * 1000);
read_hw_addr (dev, bis);
}
/* Reset the ethernet controller
*/
OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
- udelay (20);
+ udelay(20);
OUTL (dev, I82559_RESET, SCBPort);
- udelay (20);
+ udelay(20);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
/* Reset the ethernet controller
*/
OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
- udelay (20);
+ udelay(20);
OUTL (dev, I82559_RESET, SCBPort);
- udelay (20);
+ udelay(20);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
OUTW (dev, EE_ENB | dataval, SCBeeprom);
- udelay (1);
+ udelay(1);
OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
- udelay (1);
+ udelay(1);
}
OUTW (dev, EE_ENB, SCBeeprom);
for (i = 15; i >= 0; i--) {
OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
- udelay (1);
+ udelay(1);
retval = (retval << 1) |
((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
OUTW (dev, EE_ENB, SCBeeprom);
- udelay (1);
+ udelay(1);
}
/* Terminate the EEPROM access. */
SMC_SELECT_BANK(dev, 0);
SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
- udelay (10);
+ udelay(10);
/* Disable transmit and receive functionality */
SMC_outw(dev, 0, LAN91C96_RCR);
/* wait for MMU getting ready (low) */
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay (10);
+ udelay(10);
PRINTK2("MMU ready\n");
/* wait for MMU getting ready (low) */
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay (10);
+ udelay(10);
PRINTK2 ("MMU ready\n");
}
}
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay (1); /* Wait until not busy */
+ udelay(1); /* Wait until not busy */
/* error or good, tell the card to get rid of this packet */
SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
- udelay (1); /* Wait until not busy */
+ udelay(1); /* Wait until not busy */
if (!is_error) {
/* Pass the packet up to the protocol layers. */
/* assume bank 2 selected */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
- udelay (1); /* Wait until not busy */
+ udelay(1); /* Wait until not busy */
if (++count > 200)
break;
}
SMC_SELECT_BANK (dev, 0);
/* this should pause enough for the chip to be happy */
- udelay (10);
+ udelay(10);
/* Disable transmit and receive functionality */
SMC_outw (dev, RCR_CLEAR, RCR_REG);
smc_wait_mmu_release_complete (dev);
SMC_outw (dev, MC_RESET, MMU_CMD_REG);
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
- udelay (1); /* Wait until not busy */
+ udelay(1); /* Wait until not busy */
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
but this is a place where future chipsets _COULD_ break. Be wary
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
- udelay (10);
+ udelay(10);
}
PRINTK2 ("MMU ready\n");
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
- udelay (10);
+ udelay(10);
}
PRINTK2 ("MMU ready\n");
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
SMC_outw (dev, mii_reg | bits[i], MII_REG);
- udelay (SMC_PHY_CLOCK_DELAY);
+ udelay(SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
- udelay (SMC_PHY_CLOCK_DELAY);
+ udelay(SMC_PHY_CLOCK_DELAY);
bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
SMC_outw (dev, mii_reg, MII_REG);
- udelay (SMC_PHY_CLOCK_DELAY);
+ udelay(SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
SMC_SELECT_BANK (dev, oldBank);
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
SMC_outw (dev, mii_reg | bits[i], MII_REG);
- udelay (SMC_PHY_CLOCK_DELAY);
+ udelay(SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
- udelay (SMC_PHY_CLOCK_DELAY);
+ udelay(SMC_PHY_CLOCK_DELAY);
bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
SMC_outw (dev, mii_reg, MII_REG);
- udelay (SMC_PHY_CLOCK_DELAY);
+ udelay(SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
SMC_SELECT_BANK (dev, oldBank);
uec_phy_write(mii_info, 0x04, 0x01e1);
uec_phy_write(mii_info, 0x00, 0x9140);
uec_phy_write(mii_info, 0x00, 0x1000);
- udelay (100000);
+ mdelay(100);
uec_phy_write(mii_info, 0x00, 0x2900);
uec_phy_write(mii_info, 0x14, 0x0cd2);
uec_phy_write(mii_info, 0x00, 0xa100);
uec_phy_write(mii_info, 0x04, 0x05e1);
uec_phy_write(mii_info, 0x00, 0xa100);
uec_phy_write(mii_info, 0x00, 0x2100);
- udelay (1000000);
+ mdelay(1000);
} else if (speed == SPEED_10) {
uec_phy_write(mii_info, 0x14, 0x8e40);
uec_phy_write(mii_info, 0x1b, 0x800b);
uec_phy_write(mii_info, 0x14, 0x0c82);
uec_phy_write(mii_info, 0x00, 0x8100);
- udelay (1000000);
+ mdelay(1000);
}
}
/* Now we can enable the DS1306 RTC */
immap->im_cpm.cp_pbdat |= PB_SPI_CE;
- udelay (10);
+ udelay(10);
/* Shift out the address (0) of the time in the Clock Chip */
soft_spi_send (0);
/* Now we can disable the DS1306 RTC */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
- udelay (10);
+ udelay(10);
rtc_calc_weekday(tmp); /* Determine the day of week */
/* Now we can enable the DS1306 RTC */
immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
- udelay (10);
+ udelay(10);
/* First disable write protect in the clock chip control register */
soft_spi_send (0x8F); /* send address of the control register */
/* Now disable the DS1306 to terminate the write */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
- udelay (10);
+ udelay(10);
/* Now enable the DS1306 to initiate a new write */
immap->im_cpm.cp_pbdat |= PB_SPI_CE;
- udelay (10);
+ udelay(10);
/* Next, send the address of the clock time write registers */
soft_spi_send (0x80); /* send address of the first time register */
/* Now we can disable the Clock chip to terminate the burst write */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
- udelay (10);
+ udelay(10);
/* Now we can enable the Clock chip to initiate a new write */
immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
- udelay (10);
+ udelay(10);
/* First we Enable write protect in the clock chip control register */
soft_spi_send (0x8F); /* send address of the control register */
/* Now disable the DS1306 */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
- udelay (10);
+ udelay(10);
/* Set standard MPC8xx clock to the same time so Linux will
* see the time even if it doesn't have a DS1306 clock driver.
immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
- udelay (10);
+ udelay(10);
}
/* ------------------------------------------------------------------------- */
immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
else
immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
- udelay (10);
+ udelay(10);
immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
- udelay (10);
+ udelay(10);
bitpos >>= 1; /* Shift for next bit position */
}
/* Read 8 bits here */
for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
- udelay (10);
+ udelay(10);
if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
spi_byte |= bitpos; /* Set data accordingly */
immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
- udelay (10);
+ udelay(10);
bitpos >>= 1; /* Shift for next bit position */
}
GraphicDevice *dev = &mb862xx;
HOST_WR_REG (GC_SRST, 0x1);
- udelay (500);
+ udelay(500);
video_hw_init ();
}
/* Setup clocks and memory mode for Coral-P(A) */
HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
- udelay (200);
+ udelay(200);
HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
- udelay (100);
+ udelay(100);
return dev->frameAdrs;
}
CTL_RELOAD, CTL_REG);
i = 100;
while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
- udelay (100);
+ udelay(100);
if (i == 0) {
printf ("Timeout Refreshing EEPROM registers\n");
} else {
CTL_RELOAD, CTL_REG);
timeout = 100;
while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
- udelay (100);
+ udelay(100);
if (timeout == 0) {
printf ("Timeout Reading EEPROM register %02x\n", reg);
return 0;
CTL_STORE, CTL_REG);
timeout = 100;
while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
- udelay (100);
+ udelay(100);
if (timeout == 0) {
printf ("Timeout Writing EEPROM register %02x\n", reg);
return 0;
do {
WATCHDOG_RESET();
kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
- __udelay (kv);
+ __udelay(kv);
usec -= kv;
} while(usec);
}
projects / u-boot.git / commitdiff
