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(parent: 555cf4c) | patch
clk: stm32f: fix setting of division factor for LCD_CLK
authorDario Binacchi <dario.binacchi@amarulasolutions.com>
Sat, 11 Nov 2023 10:46:18 +0000 (11:46 +0100)
committerPatrice Chotard <patrice.chotard@foss.st.com>
Fri, 15 Dec 2023 14:03:18 +0000 (15:03 +0100)
commitbd6eb5ddd715e7441d804c67f434418e172a1423
tree9878b23810c2287ba8f3578868f31c887c291de6tree | snapshot
parent555cf4c49594fba017b88e913bae1cb0992ea553commit | diff
clk: stm32f: fix setting of division factor for LCD_CLK

The value to be written to the register must be appropriately shifted,
as is correctly done in other parts of the code.

Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
drivers/clk/stm32/clk-stm32f.c diff | blob | history
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