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(parent: 1583c87) | patch
ARM: dts: k3-j721s2: Correct timer frequency
authorVignesh Raghavendra <vigneshr@ti.com>
Mon, 7 Mar 2022 09:25:51 +0000 (14:55 +0530)
committerTom Rini <trini@konsulko.com>
Mon, 11 Apr 2022 15:39:19 +0000 (11:39 -0400)
commit7262ff7e564c8b7d81f940af242c20f832ee7511
tree1f9c0de78eee845b61608d18aa74ccc7b9e34b80tree | snapshot
parent1583c87b1b813a04c95732ae8075d79b14a26eeacommit | diff
ARM: dts: k3-j721s2: Correct timer frequency

MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.

Without this delays in R5 SPL are 10x off.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi diff | blob | history
My U-Boot fork