From: Anton Staaf <robotboy@chromium.org> Date: Mon, 17 Oct 2011 23:46:04 +0000 (-0700) Subject: m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment X-Git-Tag: v2025.01-rc5-pxa1908~18761 X-Git-Url: http://git.dujemihanovic.xyz/%22/icons/right.gif/static/git-logo.png?a=commitdiff_plain;h=a8fc12eb8e7ff6a97c45d921fdf28dcaaba9c8b6;p=u-boot.git m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Jason Jin <jason.jin@freescale.com> --- diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 7c84e48471..5c9bb30835 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -207,4 +207,14 @@ void dcache_invalid(void); #endif +/* + * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer + * alignment unless the board configuration has specified a new value. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 16 +#endif + #endif /* __CACHE_H */