From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Mon, 3 Jul 2017 10:37:11 +0000 (+0800)
Subject: armv8/fsl-lsch2: correct the config description of DSPI clock divider
X-Git-Tag: v2025.01-rc5-pxa1908~6130^2~9
X-Git-Url: http://git.dujemihanovic.xyz/%22/icons/right.gif/static/%7B%7B%20%24image.RelPermalink%20%7D%7D?a=commitdiff_plain;h=bf7aecce04f0b29126b870c6d1e926bd26a681e8;p=u-boot.git

armv8/fsl-lsch2: correct the config description of DSPI clock divider

It is derived from Platform clock instead of Platform PLL frequency.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5825f9b726..43b869f1fc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -307,7 +307,7 @@ config SYS_FSL_DSPI_CLK_DIV
 	default 2
 	help
 	  This is the divider that is used to derive DSPI clock from Platform
-	  PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
+	  clock, in another word DSPI_clk = Platform_clk / this_divider.
 
 config SYS_FSL_DUART_CLK_DIV
 	int "DUART clock divider"